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IP Formats Available for Purchase
Bitstream, Netlist, Source Code, constraint files

Source Code Format(s)  
VHDL / Verilog / Matlab / C / C++ / Java / Python source codes

HDL simulation models
Bit-accurate Matlab, C or C++ simulation model

Integration Testbench    
VHDL test bench and test vectors / Test bench scripts

Reports & Documents
Code Coverage Report   
Functional Coverage Report  
Comprehensive documentation
Block level design document
User guide

Commercial Evaluation Board

Software Drivers


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An earlier yet obsolete version of Angelia is maintained for reference only, see https://angeliaplutus.github.io/